Download PDF by Gang He, Zhaoqi Sun: High-k Gate Dielectrics for CMOS Technology

By Gang He, Zhaoqi Sun

A state of the art assessment of high-k dielectric fabrics for complicated field-effect transistors, from either a basic and a technological standpoint, summarizing the newest learn effects and improvement ideas.
As such, the booklet essentially discusses the benefits of those fabrics over traditional fabrics and in addition addresses the problems that accompany their integration into latest creation applied sciences. themes lined contain downscaling limits of present transistor designs, deposition recommendations for high-k dielectric fabrics, electric characterization of the ensuing units, and an outlook in the direction of destiny transistor stacking technology.
aimed toward academia and alike, this monograph combines introductory components for rookies to the sector in addition to complicated sections with without delay acceptable suggestions for skilled researchers and builders in fabrics technology, physics and electric engineering.

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And Bersuker, G. (2005) Effects of ALD HfO2 thickness on charge trapping and mobility. Microelectron. , 80, 218. G. (2006) Nucleation and growth study of atomic layer deposited HfO2 gate dielectrics resulting in improved scaling and electron mobility. J. Appl. , 99, 023508. , and Asenov, A. (2007) Beyond SiO2 technology: simulation of the impact of high-k dielectrics on mobility. J. NonCryst. Solids, 353, 630. , and Heyns, M. (2005). High performing 8 angstrom EOT HfO2/TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown (SPER) junctions.

7ps inverter delay. IEDM Technical Digest, p. 627. , and Taur, Y. (1999) Modeling and characterization of quantization, polysilicon depletion, and direct tunelling effects in MOSFETs with ultrathin oxides. IBM J. Res. , 43, 327. L. (2001) Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: understanding the processing, structure, and physical and electrical limits. J. Appl. , 90, 2057. , and Shanware, A. (1999) Self-consistent MOSFET tunneling simulations? Trends in the gate and substrate currents and the drain-current turnaround effect with oxide scaling.

In the direct tunneling regime, the current is rather insensitive to the applied voltage or field across the oxide, so reduced voltage operation will not buy much relief. Although the gate leakage current may be at a level that is negligible compared to the on-state current of a device, it will first have an effect on the chip standby power. 3. Edge tunneling in the gate-to-drain overlap region of turned-off devices should not be a fundamental issue since one can always build up the corner oxide thickness by additional oxidation of poly-silicon after gate patterning.

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